View S3P72K8_299712.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

S3C72K8/P72K8
PRODUCT OVERVIEW
1
OVERVIEW
PRODUCT OVERVIEW
The S3C72K8 singl-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM48 (Samsung Arrageable Microcontrollers). With a two-channel comparator, up-to320-dot LCD direct drive capability, 8-bit timer/counter, watchdog timer and serial I/O, the S3C72K8 offers an excellent design solution for a wide variety of applications which require LCD functions. Up to 27 pins of the 80-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast response to internal and external events. In addition, the S3C72K8's advanced CMOS technology provides for low power consumption and a wide operating voltage range.
OTP
The S3C72K8 microcontroller is also available is OTP (one time programmable) version, S3P72K8. S3P72K8 microcontroller has an one-chop 8 Kbyte one time programmable EPROM instead of masked ROM. The S3P72K8 is comparable to S3C72K8, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C72K8/P72K8
FEATURES
Memory -- 8 K x 8-bit RAM -- 1,024 x 4-bit ROM 27 I/O Pins -- Input only: 4 pins -- I/O: 15 pins -- Output: maximum 8 pins for 1-bit level output (sharing with segment driver outputs) Comparator -- Two channel mode: internal reference (4-bit resolution) -- One channel mode: external reference LCD Controller/Driver -- 40 segments and 8 common terminals -- 3, 4 and 8 common selectable -- Internal resistor circuit for LCD bias -- All dot can be switched on/off 8-Bit Basic Timer -- 4 interval timer functions -- Watchdog timer 8-Bit Timer/Counter -- Programmable 8-bit timer -- External event counter -- Arbitrary clock frequency output -- External clock signal divider -- Serial I/O interface clock generator 8-Bit Serial I/O Interface -- 8-bit transmit/receive mode -- 8-bit receive only mode -- LSB-first or MSB-first transmission selectable -- Internal or external clock source Bit Sequential Carrier -- Support 16-bit serial data transfer in arbitrary format Instruction Execution Times -- 0.67 us at 6 MHz (minimum) -- 0.95 s at 4.19 MHz (minimum) -- 122 s at 32,768 kHz (minimum) Operating Temperature -- - 40 C to 85 C Operating Voltage Range -- 2.0 V to 5.5 V Package Type -- 80-pin QFP Two Power-Down Modes -- Idle mode (only CPU clock stops) -- Stop mode (main system oscillation stops) -- Subsystem clock stop mode Oscillation Sources -- Crystal, ceramic, or External RC for system clock -- Main system clock frequency: 0.4 MHz-6 MHz -- Subsystem clock frequency: 32,768 kHz -- CPU clock divider circuit (by 4, 8, or 64) Interrupts -- Three internal vectored interrupts: INTB, INTT0, INTS -- Four external vectored interrupts: INT0, INT1, INT4, INTK -- Two quasi-interrupts: INT2, INTW Memory-Mapped I/O Structure -- Data memory bank 15 Watch Timer -- Timer interval generation: 0.5 s, 3.9 ms at 32,768 Hz -- Four frequency outputs to BUZ pin -- Clock source generation for LCD
1-2
S3C72K8/P72K8
PRODUCT OVERVIEW
BLOCK DIAGRAM
RESET Watchdog Timer Basic Timer Interrupt Control Block
XIN XOUT XTIN XTOUT LCD Driver/ Controller Clock Stack Pointer I/O Port 2
VLC1-VLC5 COM0-COM7 SEG0-SEG31 P5.0/SEG32P5.7/SEG39 P2.0-P2.3 P3.0 P3.1 P3.2/LCDSY P3.3/CLDCK P4.0/CLO P4.1/TCL0 P4.2/TCLO0
Watch Timer
SIO P0.0/SCK/K0 P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3
Internal Interrupts Instruction Decoder
Program Counter I/O Port 3 Program Status Word I/O Port 4 Flags 8-Bit Timer/ Counter 8 Kbyte Program Memory
I/O Port 0 Arithmetic and Logic Unit
Comparator P1.0/INT0/CIN0 P1.1/INT1/CIN1 P1.2/INT2 P1.3/INT4
Input Port 1
1024 x 4-Bit Data Memory
Figure 1-1. S3C72K8 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C72K8/P72K8
PIN ASSIGNMENTS
SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32/P5.0 SEG33/P5.1 SEG34/P5.2 SEG35/P5.3 SEG36/P5.4 SEG37/P5.5 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
P5.6/SEG38 P5.7/SEG39 VLC1 VLC2 VLC3 VLC4 VLC5 P0.0/SCK/K0 P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3 VDD VSS XOUT XIN TEST XTIN XTOUT RESET P1.0/INT0/CIN0 P1.1/INT1/CIN1 P1.2/INT2 P1.3/INT4 P2.0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
S3C72K8
(80-QFP-1420C)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM7 COM6
Figure 1-2. S3C72K8 80-QFP Pin Assignment
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 COM5 COM4 COM3 COM2 COM1 COM0 TCLO0/P4.2 TCL0/P4.1 CLO/P4.0 LCDCK/P3.3 LCDSY/P3.2 P3.1 P3.0 P2.3 P2.2 P2.1
1-4
S3C72K8/P72K8
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C72K8 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. Individual pins are software configurable as opendrain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 4-bit input port. 1-bit or 4-bit read and test are possible. The 1-bit unit pull-up resistors are assigned to input pins by software. An interrupt is generated by digital input at P1.0, P1.1. Same as port 0 except that 8-bit read/write and test is possible. Circuit Type E-2 Pin Number 8 9 10 11 Share Pin K0/SCK K1/SO K2/SI K3/BUZ
P1.0 P1.1 P1.2 P1.3
I
F-4 F-4 A-3 A-3
20 21 22 23
INT0/CIN0 INT1/CIN1 INT2 INT4
P2.0-P2.3 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P5.0-P5.7 SCK SO SI BUZ K0-K3 INT0 INT1 INT2 INT4
I/O
E-2
24-27 28 29 30 31
- - - LCDSY LCDCK CLO TCL0 TCLO0 SEG32- SEG39 P0.0/K0 P0.1/K1 P0.2/K2 P0.3/K3 P0.0-P0.3 P1.0/CIN0 P1.1/CIN1 P1.2 P1.3
I/O
Same as port 0 except that port 4 is 3-bit I/O port.
E-2
32 33 34 75- 80,1,2 8 9 10 11 8-11 20 21 22 23
O I/O I/O I/O I/O I/O I I I
Output port for 1-bit data Serial I/O interface clock signal Serial data output Serial data input 2 KHz, 4 KHz, 8 KHz or 16 KHz frequency output at the watch timer clock frequency of 32.768 kHz. External interrupt. The triggering edge is selectable. External interrupts. The triggering edge for INT0 and INT1 is selectable. Quasi-interrupt with detection of rising or falling edges External interrupts with detection of rising and falling edges
H-11 E-2 E-2 E-2 E-2 E-2 F-4 A-3 A-3
1-5
PRODUCT OVERVIEW
S3C72K8/P72K8
Table 1-1. S3C72K8 Pin Descriptions (Continued) Pin Name CIN0 CIN1 LCDSY LCDCK CLO TCL0 TCLO0 SEG32- SEG39 SEG0- SEG31 COM0- COM7 VLC1-VLC5 XIN, XOUT XTIN, XTOUT VDD VSS RESET TEST Pin Type I Description 2-channel comparator input. CIN0: comparator input or external reference input CIN1: comparator input only. LCD synchronization clock output for display expansion LCD clock output for display expansion Clock output External clock input for timer/counter 0 Timer/counter 0 clock output LCD segment signal output LCD segment signal output LCD common signal output LCD power supply. Voltage dividing resistors are assignable by mask option. Crystal, ceramic or RC oscillator pins for system clock. Crystal oscillator pins for subsystem clock. Main power supply Ground Chip reset signal input Chip test signal input (must be connected to VSS) Circuit Type F-4 Pin Number 20 21 30 31 32 33 34 75- 80,1,2 43-74 35-42 3-7 15, 14 17, 18 12 13 19 16 Share Pin P1.0/INT0 P1.1/INT1 P3.2 P3.3 P4.0 P4.1 P4.2 P5.0-P5.7 - - - - - - - - -
I/O I/O I/O I/O I/O O O O - - - - - I I
E-2 E-2 E-2 E-2 E-2 H-11 H-6 H-6 - - - - - B -
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode
1-6
S3C72K8/P72K8
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD Pull-Up Resistor In N-Channel Schmitt Trigger
P-Channel In
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD Pull-Up Resistor P-Channel Pull-Up Resistor Enable
VDD
Data
P-Channel Out
In Schmitt Trigger
Output Disable
N-Channel
Figure 1-4. Pin Circuit Type A-3
Figure 1-6. Pin Circuit Type 7
1-7
PRODUCT OVERVIEW
S3C72K8/P72K8
VDD PNE Pull-up Resistor Resistor Enable P-CH Data Output Disable N-CH I/O
VDD
Schmitt Trigger
Figure 1-7. Pin Circuit Type E-2
VDD Pull-up Resistor Resistor Enable
Schmitt Trigger Digital In
I/O
EXT-REF (P1.0 only) Analog In + Comparator INT-REF Digital or Analog Selectable by Software (P1MOD)
Figure 1-8. Pin Circuit Type F-4
1-8
S3C72K8/P72K8
PRODUCT OVERVIEW
VDD
VLC1
VLC2
SEG/COM Data Output Disable
Out
VLC3
VLC4
VLC5
Figure 1-9. Pin Circuit Type H-5
1-9
PRODUCT OVERVIEW
S3C72K8/P72K8
VDD
VLC1
VLC2
SEG/COM
Out
VLC3
VLC4
VLC5
Figure 1-10. Pin Circuit Type H-6
VDD
P-CH Data Output Disable 1 N-CH Out
SEG Output Disable 2
Circuit Type H-5
Figure 1-11. Pin Circuit Type H-11
1-10
S3C72K8/P72K8
ELECTRICAL DATA
15
OVERVIEW
ELECTRICAL DATA
In this section, information on S3C72K8 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- Main system clock oscillator characteristics -- Subsystem clock oscillator characteristics -- I/O capacitance -- Comparator electrical characteristics -- A.C. electrical characteristics -- Operating voltage range Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request Miscellaneous Timing Waveforms -- A.C timing measurement points -- Clock timing measurement at XIN -- Clock timing measurement at XTIN -- TCL timing -- Input timing for RESET signal -- Input timing for external interrupts -- Serial data transfer timing
15-1
ELECTRICAL DATA
S3C72K8/P72K8
Table 15-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Output Current Low Symbol VDD VI1 VO I OH I OL Conditions - All I/O pins active - One I/O pin active All I/O pins active One I/O pin active Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 35 + 30 (Peak value) + 15 (note) All I/O port, total Operating Temperature Storage Temperature TA Tstg - - + 100 (Peak value) + 60 (note) - 40 to + 85 - 65 to + 150
Duty . C C
Units V V V mA mA
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value x
15-2
S3C72K8/P72K8
ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage VOH1 Conditions Ports 2, 3, P4.0 and P4.2 Ports 0, 1, P4.1 and RESET XIN, XOUT and XTIN Ports 2, 3, P4.0 and P4.2 Ports 0, 1, P4.1 and RESET XIN, XOUT and XTIN VDD = 4.5 V to 5.5 V IOH = - 3 mA Ports 0, 2, 3 and 4 VDD = 4.5 V to 5.5 V IOH = - 100 A Ports 5 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 0, 2, 3 and 4 VOL2 VDD = 4.5 V to 5.5 V IOH = - 100 A Ports 5 VIN = VDD All input pins except those specified below for ILIH2 VIN = VDD XIN, XOUT and XTIN VIN = 0 V All input pins except XIN, XOUT, XTIN, and RESET ILIL2 Output High Leakage Current Output Low Leakage Current ILOH VIN = 0 V XIN, XOUT and XTIN VO = VDD All output pins VO = 0 V All output pins - - - 20 3 A - - - - 1 VDD - 2.0 VDD - 0.4 Min 0.7 VDD 0.8 VDD VDD - 0.1 - - Typ - Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 - V V Units V
VOH2
VDD - 2.0
-
-
Output Low Voltage
VOL1
-
0.4
2
V
Input High Leakage Current
ILIH1
-
-
3
A
ILIH2 Input Low Leakage Current ILIL1
20 -3 A
ILOL
-
-
-3
A
15-3
ELECTRICAL DATA
S3C72K8/P72K8
Table 15-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Pull-Up Resistor Symbol RLI Conditions VIN = 0 V; VDD = 5 V 10 % Ports 0-4 VDD = 3 V 10 % RL2 VIN = 0 V; VDD = 5 V 10 % RESET VDD = 3 V 10 % LCD Voltage Dividing Resistor |VDD-COMi| Voltage Drop (i = 0-7) |VDD-SEGx| Voltage Drop (x = 0-39) VLC1 Output Voltage VLC2 Output Voltage VLC3 Output Voltage VLC4 Output Voltage RLCD - 300 40 400 60 800 90 k Min 15 30 150 Typ 40 80 220 Max 80 200 350 Units k
VDC
VDD = 2.7 V to 5.5 V - 15 A per common pin VDD = 2.7 V to 5.5 V - 15 A per segment pin VDD = 2.0 V to 5.5 V (1) LCD clock = 0 Hz, VLC5 = 0 V
-
-
120
mV
VDS
-
-
120
VLC2 VLC3 VLC4 VLC5
0.8 VDD- 0.2 0.6 VDD- 0.2 0.4 VDD- 0.2 0.2 VDD- 0.2
0.8 VDD 0.6 VDD 0.4 VDD 0.2 VDD
0.8 VDD+ 0.2 0.6 VDD+ 0.2 0.4 VDD+ 0.2 0.2 VDD+ 0.2
V
15-4
S3C72K8/P72K8
ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (2) Conditions VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD2 (2) Idle mode VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD3 (3) IDD4 (3) IDD5 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz Min - Typ 3.5 2.5 1.8 1.3 1.3 1.2 Max 8.0 5.5 4.0 3.0 2.5 1.8 Units mA
6.0 MHz 4.19 MHz -
0.5 0.4 15 6 2.5
1.5 1.0 30 15 5
VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% VDD = 5 V 10% VDD = 3 V 10% SCMOD = 0100B SCMOD = 0000B XTIN = 0V
0.5 0.2 0.1
3 3 2
NOTES: 1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, output port drive currents, comparator. 2. Data includes power consumption for subsystem clock oscillation. 3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 4. Every values in this table is measured when the power control register (PCON) is set to "0011B".
15-5
ELECTRICAL DATA
S3C72K8/P72K8
Table 15-3. Main System Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 2.0 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration
XIN XOUT
Parameter Oscillation frequency (1)
Test Condition -
Min 0.4
Typ -
Max 6.0
Units MHz
C1
C2
Stabilization time (2)
Stabilization occurs when VDD is equal to the minimum oscillator voltage range. -
-
-
4
ms
Crystal Oscillator
XIN
XOUT
Oscillation frequency (1)
0.4
-
6.0
MHz
C1
C2
Stabilization time (2)
VDD = 4.5 V to 5.5 V VDD = 2.7 V to 4.5 V -
- - 0.4
- - -
10 30 6.0
ms
External Clock
XIN
XOUT
XIN input frequency (1)
MHz
XIN input high and low level width (tXH, tXL) RC Oscillator
XIN R XOUT
- R = 10 k, VDD = 5 V
83.3 -
- 2
1250 -
ns MHz
Frequency
R = 30 k, VDD = 3 V
NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2.
-
1
-
Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
15-6
S3C72K8/P72K8
ELECTRICAL DATA
Table 15-4. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 2.0 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration
XTIN XTOUT
Parameter Oscillation frequency (1)
Test Condition -
Min 32
Typ 32.768
Max 35
Units kHz
C1
C2
Stabilization time (2)
VDD = 4.5 V to 5.5 V VDD = 2.0 V to 4.5 V -
- - 32
1.0 - -
2 10 100
s
External Clock
XTIN XTOUT
XTIN input frequency (1)
kHz
XTIN input high and low level width (tXTL, tXTH)
-
5
-
15
s
NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
15-7
ELECTRICAL DATA
S3C72K8/P72K8
Table 15-5. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF
Table 15-6. Comparator Electrical Characteristics (TA = - 40 C + 85 C, VDD = 4.0 V to 5.5 V) Parameter Input Voltage Range Reference Voltage Range Input Voltage Accuracy Input Leakage Current Symbol - VREF VCIN ICIN, IREF Condition - Min 0 0 - -3 Typ - Max VDD VDD 150 3 Units V V mV A
15-8
S3C72K8/P72K8
ELECTRICAL DATA
Table 15-7. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Instruction Cycle Time (note) Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V With subsystem clock (fxt) TCL0 Input Frequency TCL0 Input High, Low Width f TI0, f TI1 VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V tTIH0, tTIL0 tTIH1, tTIL1 tKCY VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V SCK Cycle Time VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source SCK High, Low Width tKH, tKL Internal SCK source VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source SI Setup Time to SCK High tSIK VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source SI Hold Time to SCK High tKSI Internal SCK source VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source 500 400 600 500 400 - - ns 150 150 tKCY/2 - 150 100 - - ns tKCY/2 - 50 1600 3800 325 - - ns 650 3200 0.48 1.8 800 - - ns - Min 0.67 0.95 114 0 Typ - - 122 - Max 64 64 125 1.5 1 - s MHz Units s
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
15-9
ELECTRICAL DATA
S3C72K8/P72K8
Table 15-7. A.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Output Delay for SCK to SO Symbol tKSO Conditions VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 2.0 V to 5.5 V External SCK source Internal SCK source Interrupt Input High, Low Width RESET Input Low Width tINTH, tINTL tRSL INT0, INT1, INT2, INT4, K0-K3 Input 10 10 - - 1000 - - s s 250 1000 Min - Typ - Max 300 Units ns
CPU Clock 1.5 MHz
Main Oscillator Frequency (Divided by 4) 6 MHz
1.05 MHz
4.2 MHz
15.6 kHz 1 2 3 4 5 6 7
2.0 V 2.7 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 15-1. Standard Operating Voltage Range
15-10
S3C72K8/P72K8
ELECTRICAL DATA
Table 15-8. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 2.0 V - Released by RESET Released by interrupt Min 2.0 - 0 - - Typ - 0.1 - 217 / fx
(2)
Max 5.5 10 - - -
Unit V A s ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
15-11
ELECTRICAL DATA
S3C72K8/P72K8
TIMING WAVEFORMS
Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Normal Mode
~ ~ ~ ~
VDD
VDDDR Execution of STOP Instrction RESET tWAIT tSREL
Figure 15-2. Stop Mode Release Timing When Initiated By RESET
Idle Mode
~ ~ ~ ~
Stop Mode Data Retention Mode
Normal Mode
VDD
VDDDR Execution of STOP Instrction
tSREL
tWAIT Power-down Mode Terminating Signal (Interrupt Request)
Figure 15-3. Stop Mode Release Timing When Initiated By Interrupt Request
15-12
S3C72K8/P72K8
ELECTRICAL DATA
0.8 VDD Measurement Points 0.2 VDD
0.8 VDD
0.2 VDD
Figure 15-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx tXL tXH
XIN
VDD - 0.1 V 0.1 V
Figure 15-5. Clock Timing Measurement at XIN
1/fxt tXTL tXTH
XTIN
VDD - 0.1 V 0.1 V
Figure 15-6. Clock Timing Measurement at XTIN
15-13
ELECTRICAL DATA
S3C72K8/P72K8
1/fTI tTIL tTIH
TCL0
0.8 VDD 0.2 VDD
Figure 15-7. TCL Timing
tRSL
RESET 0.2 VDD
Figure 15-8. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1, 2, 4, K0 to K3
0.8 VDD 0.2 VDD
Figure 15-9. Input Timing for External Interrupts and Quasi-Interrupts
15-14
S3C72K8/P72K8
ELECTRICAL DATA
tKCY tKL SCK 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKSO tKH
SO
Output Data
Figure 15-10. Serial Data Transfer Timing
15-15
S3C72K8/P72K8
MECHANICAL DATA
16
OVERVIEW
MECHANICAL DATA
The S3C72K8 microcontroller is currently available in a 80-pin QFP package.
23.90 0.30 20.00 0.20 0-8
+ 0.10
0.15 - 0.05
17.90 0.30
14.00 0.20
80-QFP-1420C
0.80 0.20 #1 0.80 0.35 + 0.10 0.15 MAX
0.10 MAX
#80
0.05 MIN (0.80) 2.65 0.10 3.00 MAX
0.80 0.20
NOTE: Dimensions are in millimeters.
Figure 16-1. 80-QFP-1420C Package Dimensions
16-1
S3C72K8/P72K8
S3P72K8 OTP
17
OVERVIEW
S3P72K8 OTP
The S3P72K8 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72K8 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P72K8 is fully compatible with the S3C72K8, both in function and in pin configuration except ROM size. Because of its simple programming requirements, the S3P72K8 is ideal for use as an evaluation chip for the S3C72K8.
17-1
S3P72K8 OTP
S3C72K8/P72K8
SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32/P5.0 SEG33/P5.1 SEG34/P5.2 SEG35/P5.3 SEG36/P5.4 SEG37/P5.5 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM7 COM6
P5.6/SEG38 P5.7/SEG39 VLC1 VLC2 VLC3 VLC4 VLC5 P0.0/SCK/K0 P0.1/SO/K1 SDAT/P0.2/SI/K2 SCLK/P0.3/BUZ/K3 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET RESET P1.0/INT0/CIN0 P1.1/INT1/CIN1 P1.1/INT2 P1.3/INT4 P2.0
S3P72K8
(80-QFP-1420C)
Figure 17-1. S3P72K8 Pin Assignments (80-QFP Package)
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 COM5 COM4 COM3 COM2 COM1 COM0 TCLO0/P4.2 TCL0/P4.1 CLO/P4.0 LCDCK/P3.3 LCDSY/P3.2 P3.1 P3.0 P2.3 P2.2 P2.1
17-2
S3C72K8/P72K8
S3P72K8 OTP
Table 17-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P0.2 Pin Name SDAT Pin No. 10 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip Initialization Logic power supply pin. VDD should be tied to +5 V during programming.
P0.3 TEST
SCLK VPP
11 16
I I
RESET VDD/VSS
RESET VDD/VSS
19 12/13
I I
Table 17-2. Comparison of S3P72K8 and S3C72K8 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 8-Kbyte EPROM 2.0 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5V 80 QFP User Program 1 time 80 QFP Programmed at the factory S3P72K8 S3C72K8 8-Kbyte mask ROM 2.0 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P72K8, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 17-3 below. Table 17-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/ MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode
NOTE: "0" means Low level; "1" means High level.
17-3
S3P72K8 OTP
S3C72K8/P72K8
NOTES
17-4

▲Up To Search▲

Price & Availability of S3P72K8

	To Download S3P72K8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .